1. Field of the Invention
The present invention relates to an IC test system for measuring IC devices, and more particularly to an IC test system for the case in which window strobe decisions extending over a plurality of test cycles are executed.
This application is based on patent application No. Hei 9142764 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
Window strobe decision is made for deciding the state of an output signal from an IC device for measuring whether or not a manufactured IC device is outputting the operational signals as it was designed, in a time period which is prescribed by two strobe signals. FIG. 7 is a diagram showing an example of the construction for the IC test system which decides window strobe decisions for an IC device which is to be measured.
In FIG. 7, the reference symbols 1, 2-1 and 2-2, 3-1 and 3-2, and 4-1 and 4-2 represent a device to be measured, comparator circuits, strobe generating circuits, and decision circuits, respectively.
In this IC test circuit, an output signal(a) from the device to be measured 1 is respectively level compared at voltage levels b-1 and b-2, which are to become as references in the comparator circuits 2-1 and 2-2 and are input to the decision circuits 4-1 and 4-2, respectively.
On the other hand, in order to perform a window strobe decision, a test cycle signal(d) and address(e) are input to the strobe generating circuits 3-1 and 3-2, and based on this signal, the strobe generating circuits 3-1 and 3-2 which output a start strobe that becomes a start signal and an end strobe that becomes an end signal f-1, f-2 respectively and output control signals g-1, g-2 to the decision circuits 4-1 and 4-2, for controlling the decision circuits 4-1, 4-2.
On the other hand, window strobe decisions are performed in the decision circuits 4-1, 4-2, with respect to output signals c-1, c-2 from the comparator circuits 2-1, 2-2, using the strobe signals f-1, f-2 and the control signals g-1, g-2 from the strobe generating circuits 3-1, 3-2, and outputs decision signals h-1, h-2.
Next, an operational example of the IC test system of FIG. 7 will be described with reference to the accompanying FIGS. 8 and 9. Furthermore, FIG. 8 is a diagram showing an example of the operating waveforms for the IC test system indicated in FIG. 7, and FIG. 9 is a figure showing an operation table which summarizes the operations, with respect to the address(e) of the strobe generating circuits 3-1 and 3-2.
In FIG. 8,(1) represents the of the output (a) from the device to be measured 1 and the waveforms of the voltage level b-1 and the voltage level b-2 which are input to the comparator circuits 2-1, 2-2 of FIG. 7.
In addition, (2) and (3) respectively represents output signals c-1, c-2 from the comparator circuits 2-1, 2-2, and (4) and (5) represent the test cycle signal(d) and the address(e) which are input to the strobe generating circuits 3-1, 3-2 respectively. (6)-(9) respectively represent the strobe signals f-1, f-2 and the waveform diagrams of the control signals g-1, g-2 output from the strobe generating circuits 3-1, 3-2. In addition, (10),(11) respectively represents the waveform diagram of the window strobe waveform which is generated inside the decision circuits 4-1, 4-2.
Here, when the address(e) is at "0" as indicated in (5) of FIG. 8, the strobe generating circuit 3-1 operates as a window start strobe and generates a start strobe which has been timing-corrected at the voltage level b-1. Moreover, here "the timing-corrected strobe signal" means that the strobe signal is generated with a timing which has been described beforehand, in response to the various voltages. Specifically, in the example of FIG. 8, timings which are corrected at each voltage level b-1, b-2 are stored in the strobe generating circuit 3-1, and timing corrections are made for generating strobe signals, based on this content of the memory.
Further, when the address(e) is "1" , the strobe generating circuit 3-1 operates as a window start strobe and performs the generation of a start strobe for which timing correction has been made at the voltage level b-2 of FIG. 8. When the address(e) is "2" or "3", this strobe generating circuit 3-1 does not operate.
On the other hand, when the address(e) is "0", "1" or "2", the strobe generating circuit 3-2 does not operate but instead operates as a window end strobe, when the address(e) is "3", FIG. 9 is a summary of the operations for each of the strobe generating circuits 3-1, 3-2 with respect to this address(e). When a circuit does not operate, it is marked as "-" in FIG. 9.
Further, with respect to output signal(a) from the device 1 to be measured which is indicated in (1) of FIG. 7, the comparator circuits 2-1, 2-2 output the results of the comparison at voltage levels b-1, b-2 as signals(2),(3).
Next, the test cycle signal(d) goes from the first cycle through the eighth cycle as in (4),(5) of FIG. 8, and the operation of the IC test system for the case in which the address(e) changes to 0, 2, 2, 3, 1, 2, 2 and 3, in response to the test cycle, is described as follows.
First, in the comparator 2-1 for the first test cycle, in order to decide the signal(2) which has been output/compared at the voltage level b-1, the address(e) goes to "0", and the strobe generating circuit 3-1 outputs start strobe .alpha.1 which has timing-corrected at the level b-1 and a control signal "A", which signifies the window strobe start in the decision circuit 4-1.
In the second and third test cycles, since the window strobe decision becomes one which extends over a plurality of test cycles, the address(e) goes to "2".
In the fourth cycle, in order to end the window strobe, the address(e) goes to "3", and the strobe generating circuit 3-2 outputs an end strobe .alpha.2 and a control signal "B" , which signifies window strobe end in the respective decision circuits 4-1 and 4-2.
Furthermore, in the comparator circuit 2-2 for the fifth cycle, the address(e) goes to "1" for deciding a signal(3) which has been compared/output at the voltage level b-2, and the strobe generating circuit 3-1 outputs a start strobe .alpha.3 which has been timing-corrected at the level b-2 and a control signal(C) which signifies window strobe start at the decision circuit 4-2.
In the sixth and seventh cycles, since the decision becomes a window strobe decision which extends over a plurality of testing cycles, the address(e) goes to "2".
In the eighth cycle, in order to end window strobe, the address(e) goes to "3", and the strobe generating circuit 3-2 outputs an end strobe .alpha.4 and a control signal(B), which signifies window strobe finish at respective decision circuits.
In addition, such strobe windows as those indicated in (10) and (11) are generated within the decision circuits 4-1 and 4-2, based on the strobe signals f-1, f-2 and the control signals g-1, g-2 from the strobe circuits 3-1, 3-2, and a window strobe decisions are made.
Here, the normal window strobe decision using IC test system is completed without extending over to a plurality of test cycles. However, depending on the case, there may be cases in which the decision will be completed after several cycles from the test cycle which the window strobe started. In a normal IC test system, since consideration has not been given to window strobe decision which extends over to a plurality of test cycles in this way, even if "3" which signifies window strobe end similar to the address(e) as shown in (5) of FIG. 8 has been sent, it is incapable of concluding as to which of the voltage levels the window strobe decision end corresponds.
For this reason, since with respect to which voltage level the strobe decision starts can be known in FIG. 8, at the window strobe start of the first cycle and at the window strobe start of the fifth cycle, the start strobe which has been optimally timing-corrected at the voltage level b-1 or b-2 can be output. However, since it is unclear as to what voltage level the end of the window strobe decision corresponds, at the end of window strobe for the fourth test cycle and at the end of window strobe of the eighth cycle, outputting of end strobe which has timing-corrected in response to the voltage level cannot be output.
That is, in an ordinary IC test system, since it is incapable of deciding as to at which voltage level of window strobe decision will end for the case in which window strobe decision extends over a plurality of test cycles, in a strobe generating circuit, an end strobe which has been optimally timing-corrected in response to the voltage level cannot be generated. As a result, there is the problem that appropriate measurement results cannot be obtained.